Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\ahb_hyperram.vhd D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\gowin_clkdiv\gowin_clkdiv.vhd D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\gowin_empuvhdl\gowin_empu.vhd D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\gowin_pllvrvhdl\gowin_pllvr.vhd D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\hyperram_memory_interfacevhdl\hyperram_memory_interface.vhd D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\main.vhd |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.03 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Fri Mar 25 11:47:07 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_EMPU_Template |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 3s, Peak memory usage = 165.770MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.232s, Peak memory usage = 165.770MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 165.770MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 165.770MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 165.770MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 165.770MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 165.770MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 165.770MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 165.770MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 165.770MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 165.770MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.801s, Peak memory usage = 165.770MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 165.770MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 165.770MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 4s, Peak memory usage = 165.770MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 33 |
| Embedded Port | 13 |
| I/O Buf | 45 |
| IBUF | 20 |
| OBUF | 8 |
| TBUF | 3 |
| IOBUF | 14 |
| Register | 1193 |
| DFFE | 345 |
| DFFRE | 80 |
| DFFP | 4 |
| DFFPE | 6 |
| DFFC | 321 |
| DFFCE | 382 |
| DFFNCE | 16 |
| DL | 32 |
| DLNCE | 6 |
| DLNPE | 1 |
| LUT | 1303 |
| LUT2 | 218 |
| LUT3 | 607 |
| LUT4 | 478 |
| ALU | 45 |
| ALU | 45 |
| INV | 10 |
| INV | 10 |
| IOLOGIC | 30 |
| IDES4 | 8 |
| OSER4 | 12 |
| IODELAY | 10 |
| BSRAM | 4 |
| SP | 4 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCEN | 1 |
| PLLVR | 1 |
| User Flash | 1 |
| FLASH256K | 1 |
| EMCU | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1358(1313 LUTs, 45 ALUs) / 4608 | 29% |
| Register | 1193 / 3609 | 33% |
| --Register as Latch | 39 / 3609 | 1% |
| --Register as FF | 1154 / 3609 | 32% |
| BSRAM | 4 / 10 | 40% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| sys_clk | Base | 37.037 | 27.0 | 0.000 | 18.519 | sys_clk_ibuf/I | ||
| S_read_enable | Base | 20.000 | 50.0 | 0.000 | 10.000 | u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q | ||
| nWR_d | Base | 20.000 | 50.0 | 0.000 | 10.000 | nWR_ibuf/O | ||
| u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk | Generated | 6.289 | 159.0 | 0.000 | 3.145 | sys_clk_ibuf/I | sys_clk | u_Gowin_PLLVR/pllvr_inst/CLKOUT |
| u_Gowin_PLLVR/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 6.289 | 159.0 | 0.000 | 3.145 | sys_clk_ibuf/I | sys_clk | u_Gowin_PLLVR/pllvr_inst/CLKOUTP |
| u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 12.579 | 79.5 | 0.000 | 6.289 | sys_clk_ibuf/I | sys_clk | u_Gowin_PLLVR/pllvr_inst/CLKOUTD |
| u_Gowin_PLLVR/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 18.868 | 53.0 | 0.000 | 9.434 | sys_clk_ibuf/I | sys_clk | u_Gowin_PLLVR/pllvr_inst/CLKOUTD3 |
| u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk | Generated | 12.579 | 79.5 | 0.000 | 6.289 | u_Gowin_PLLVR/pllvr_inst/CLKOUT | u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk | u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | sys_clk | 27.0(MHz) | 67.0(MHz) | 5 | TOP |
| 2 | u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk | 79.5(MHz) | 135.6(MHz) | 5 | TOP |
| 3 | u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk | 79.5(MHz) | 116.0(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -7.362 |
| Data Arrival Time | 637.412 |
| Data Required Time | 630.050 |
| From | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0 |
| To | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_12_s0 |
| Launch Clk | sys_clk[F] |
| Latch Clk | S_read_enable[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 629.630 | 0.000 | sys_clk | |||
| 629.630 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 630.612 | 0.982 | tINS | RR | 305 | sys_clk_ibuf/O |
| 630.974 | 0.363 | tNET | RR | 1 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/CLK |
| 631.433 | 0.458 | tC2Q | RF | 2 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q |
| 631.913 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s35/I1 |
| 633.012 | 1.099 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s35/F |
| 633.492 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s33/I2 |
| 634.314 | 0.822 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s33/F |
| 634.794 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s32/I0 |
| 635.826 | 1.032 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s32/F |
| 636.306 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s31/I3 |
| 636.932 | 0.626 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n509_s31/F |
| 637.412 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_12_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 630.000 | 0.000 | S_read_enable | |||
| 630.000 | 0.000 | tCL | FF | 32 | u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q |
| 630.480 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_12_s0/G |
| 630.450 | -0.030 | tUnc | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_12_s0 | ||
| 630.050 | -0.400 | tSu | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_12_s0 |
| Clock Skew: | -0.865 |
| Setup Relationship: | 0.370 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 3.579, 55.597%; route: 2.400, 37.283%; tC2Q: 0.458, 7.120% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:| Slack | -7.362 |
| Data Arrival Time | 637.412 |
| Data Required Time | 630.050 |
| From | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_13_s0 |
| To | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_13_s0 |
| Launch Clk | sys_clk[F] |
| Latch Clk | S_read_enable[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 629.630 | 0.000 | sys_clk | |||
| 629.630 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 630.612 | 0.982 | tINS | RR | 305 | sys_clk_ibuf/O |
| 630.974 | 0.363 | tNET | RR | 1 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_13_s0/CLK |
| 631.433 | 0.458 | tC2Q | RF | 2 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_13_s0/Q |
| 631.913 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s35/I1 |
| 633.012 | 1.099 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s35/F |
| 633.492 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s33/I2 |
| 634.314 | 0.822 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s33/F |
| 634.794 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s32/I0 |
| 635.826 | 1.032 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s32/F |
| 636.306 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s31/I3 |
| 636.932 | 0.626 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n508_s31/F |
| 637.412 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_13_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 630.000 | 0.000 | S_read_enable | |||
| 630.000 | 0.000 | tCL | FF | 32 | u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q |
| 630.480 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_13_s0/G |
| 630.450 | -0.030 | tUnc | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_13_s0 | ||
| 630.050 | -0.400 | tSu | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_13_s0 |
| Clock Skew: | -0.865 |
| Setup Relationship: | 0.370 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 3.579, 55.597%; route: 2.400, 37.283%; tC2Q: 0.458, 7.120% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:| Slack | -7.362 |
| Data Arrival Time | 637.412 |
| Data Required Time | 630.050 |
| From | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_16_s0 |
| To | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_16_s0 |
| Launch Clk | sys_clk[F] |
| Latch Clk | S_read_enable[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 629.630 | 0.000 | sys_clk | |||
| 629.630 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 630.612 | 0.982 | tINS | RR | 305 | sys_clk_ibuf/O |
| 630.974 | 0.363 | tNET | RR | 1 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_16_s0/CLK |
| 631.433 | 0.458 | tC2Q | RF | 2 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_16_s0/Q |
| 631.913 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s35/I1 |
| 633.012 | 1.099 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s35/F |
| 633.492 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s33/I2 |
| 634.314 | 0.822 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s33/F |
| 634.794 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s32/I0 |
| 635.826 | 1.032 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s32/F |
| 636.306 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s31/I3 |
| 636.932 | 0.626 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n505_s31/F |
| 637.412 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_16_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 630.000 | 0.000 | S_read_enable | |||
| 630.000 | 0.000 | tCL | FF | 32 | u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q |
| 630.480 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_16_s0/G |
| 630.450 | -0.030 | tUnc | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_16_s0 | ||
| 630.050 | -0.400 | tSu | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_16_s0 |
| Clock Skew: | -0.865 |
| Setup Relationship: | 0.370 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 3.579, 55.597%; route: 2.400, 37.283%; tC2Q: 0.458, 7.120% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:| Slack | -7.362 |
| Data Arrival Time | 637.412 |
| Data Required Time | 630.050 |
| From | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_18_s0 |
| To | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0 |
| Launch Clk | sys_clk[F] |
| Latch Clk | S_read_enable[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 629.630 | 0.000 | sys_clk | |||
| 629.630 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 630.612 | 0.982 | tINS | RR | 305 | sys_clk_ibuf/O |
| 630.974 | 0.363 | tNET | RR | 1 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_18_s0/CLK |
| 631.433 | 0.458 | tC2Q | RF | 2 | u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_18_s0/Q |
| 631.913 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s35/I1 |
| 633.012 | 1.099 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s35/F |
| 633.492 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s33/I2 |
| 634.314 | 0.822 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s33/F |
| 634.794 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s32/I0 |
| 635.826 | 1.032 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s32/F |
| 636.306 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s31/I3 |
| 636.932 | 0.626 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n503_s31/F |
| 637.412 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 630.000 | 0.000 | S_read_enable | |||
| 630.000 | 0.000 | tCL | FF | 32 | u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q |
| 630.480 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0/G |
| 630.450 | -0.030 | tUnc | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0 | ||
| 630.050 | -0.400 | tSu | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0 |
| Clock Skew: | -0.865 |
| Setup Relationship: | 0.370 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 3.579, 55.597%; route: 2.400, 37.283%; tC2Q: 0.458, 7.120% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:| Slack | -6.885 |
| Data Arrival Time | 636.935 |
| Data Required Time | 630.050 |
| From | u_Gowin_AHB_HyperRAM_Top/S_ahb_address_2_s0 |
| To | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_0_s0 |
| Launch Clk | sys_clk[F] |
| Latch Clk | S_read_enable[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 629.630 | 0.000 | sys_clk | |||
| 629.630 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 630.612 | 0.982 | tINS | RR | 305 | sys_clk_ibuf/O |
| 630.974 | 0.363 | tNET | RR | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_address_2_s0/CLK |
| 631.433 | 0.458 | tC2Q | RF | 143 | u_Gowin_AHB_HyperRAM_Top/S_ahb_address_2_s0/Q |
| 631.913 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s43/I2 |
| 632.735 | 0.822 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s43/F |
| 633.215 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s33/I0 |
| 633.364 | 0.149 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s33/O |
| 633.844 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s36/I0 |
| 634.876 | 1.032 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s36/F |
| 635.356 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s35/I1 |
| 636.455 | 1.099 | tINS | FF | 1 | u_Gowin_AHB_HyperRAM_Top/n521_s35/F |
| 636.935 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 630.000 | 0.000 | S_read_enable | |||
| 630.000 | 0.000 | tCL | FF | 32 | u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q |
| 630.480 | 0.480 | tNET | FF | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_0_s0/G |
| 630.450 | -0.030 | tUnc | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_0_s0 | ||
| 630.050 | -0.400 | tSu | 1 | u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_0_s0 |
| Clock Skew: | -0.865 |
| Setup Relationship: | 0.370 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 3.102, 52.044%; route: 2.400, 40.266%; tC2Q: 0.458, 7.690% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |