Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\progs\GoWin\Gowin_V1.9.8_Education\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v
D:\progs\GoWin\Gowin_V1.9.8_Education\IDE\ipcore\HYPERRAM_EMB\data\hpram_code_166.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8 Education
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Mar 08 16:15:59 2022
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module HyperRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 30.227MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 30.227MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 30.227MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 30.227MB
    Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 30.227MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 30.227MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 30.227MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 30.227MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 30.227MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.225s, Peak memory usage = 30.227MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 30.227MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 30.227MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 45.156MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.338s, Peak memory usage = 45.156MB
Generate output files:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.292s, Peak memory usage = 45.156MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 45.156MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 99
Embedded Port 13
I/O Buf 112
    IBUF 64
    OBUF 39
    IOBUF 9
Register 677
    DFFE 208
    DFFRE 80
    DFFP 3
    DFFPE 3
    DFFC 229
    DFFCE 154
LUT 740
    LUT2 168
    LUT3 349
    LUT4 223
ALU 31
    ALU 31
INV 7
    INV 7
IOLOGIC 30
    IDES4 8
    OSER4 12
    IODELAY 10
CLOCK 3
    DLL 1
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 778(747 LUTs, 31 ALUs) / 4608 17%
Register 677 / 3612 19%
  --Register as Latch 0 / 3612 0%
  --Register as FF 677 / 3612 19%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 135.6(MHz) 5 TOP
2 u_hpram_top/clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 135.6(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.623
Data Arrival Time 8.322
Data Required Time 10.945
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s17/I1
3.382 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n315_s17/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s13/I2
4.684 0.822 tINS FF 5 u_hpram_top/u_hpram_sync/n315_s13/F
5.164 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s2/I1
6.263 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n389_s2/F
6.743 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s1/I1
7.842 1.099 tINS FF 1 u_hpram_top/u_hpram_sync/n389_s1/F
8.322 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/count_0_s0/CLK
10.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 2.886
Data Arrival Time 8.059
Data Required Time 10.945
From u_hpram_top/u_hpram_sync/cs_memsync_0_s0
To u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK
1.803 0.458 tC2Q RF 9 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
3.382 1.099 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s11/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s9/I1
4.961 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n359_s9/F
5.441 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n326_s13/I0
6.473 1.032 tINS FF 1 u_hpram_top/u_hpram_sync/n326_s13/F
6.953 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n326_s12/I3
7.579 0.626 tINS FF 1 u_hpram_top/u_hpram_sync/n326_s12/F
8.059 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0/CLK
10.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.856, 57.430%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 2.886
Data Arrival Time 8.059
Data Required Time 10.945
From u_hpram_top/u_hpram_sync/cs_memsync_0_s0
To u_hpram_top/u_hpram_sync/flag_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK
1.803 0.458 tC2Q RF 9 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
3.382 1.099 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s11/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s9/I1
4.961 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n359_s9/F
5.441 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s8/I0
6.473 1.032 tINS FF 1 u_hpram_top/u_hpram_sync/n348_s8/F
6.953 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s5/I3
7.579 0.626 tINS FF 1 u_hpram_top/u_hpram_sync/n348_s5/F
8.059 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/flag_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/flag_1_s0/CLK
10.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/flag_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.856, 57.430%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 2.900
Data Arrival Time 8.045
Data Required Time 10.945
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s17/I1
3.382 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n315_s17/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s13/I2
4.684 0.822 tINS FF 5 u_hpram_top/u_hpram_sync/n315_s13/F
5.164 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s2/I1
6.263 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n389_s2/F
6.743 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n388_s1/I2
7.565 0.822 tINS FF 1 u_hpram_top/u_hpram_sync/n388_s1/F
8.045 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/count_1_s0/CLK
10.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.842, 57.341%; route: 2.400, 35.819%; tC2Q: 0.458, 6.840%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 2.967
Data Arrival Time 7.978
Data Required Time 10.945
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/flag_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s17/I1
3.382 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n315_s17/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s13/I2
4.684 0.822 tINS FF 5 u_hpram_top/u_hpram_sync/n315_s13/F
5.164 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s8/I0
6.196 1.032 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s8/F
6.676 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s6/I2
7.498 0.822 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s6/F
7.978 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/flag_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/flag_0_s0/CLK
10.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/flag_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.775, 56.909%; route: 2.400, 36.181%; tC2Q: 0.458, 6.910%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%