Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\progs\GoWin\Gowin_V1.9.8_Education\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v D:\progs\GoWin\Gowin_V1.9.8_Education\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.8 Education |
Part Number | GW1NSR-LV4CQN48PC6/I5 |
Device | GW1NSR-4C |
Created Time | Thu Jan 27 11:57:48 2022 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 30.234MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 30.234MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 30.234MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 30.234MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 30.234MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 30.234MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 30.234MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 30.234MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 30.234MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 30.234MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 30.234MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 30.234MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.922s, Peak memory usage = 43.434MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 43.434MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 43.434MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 43.434MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 136 |
I/O Buf | 136 |
    IBUF | 41 |
    OBUF | 95 |
Register | 127 |
    DFFP | 1 |
    DFFPE | 2 |
    DFFC | 49 |
    DFFCE | 59 |
    DFFNCE | 16 |
LUT | 143 |
    LUT2 | 31 |
    LUT3 | 59 |
    LUT4 | 53 |
INV | 2 |
    INV | 2 |
BSRAM | 4 |
    SP | 4 |
Black Box | 1 |
    EMCU | 1 |
User Flash | 1 |
    FLASH256K | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 145(145 LUTs, 0 ALUs) / 4608 | 3% |
Register | 127 / 3573 | 4% |
  --Register as Latch | 0 / 3573 | 0% |
  --Register as FF | 127 / 3573 | 4% |
BSRAM | 4 / 10 | 40% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
sys_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | sys_clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | sys_clk | 100.0(MHz) | 67.0(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -2.468 |
Data Arrival Time | 8.532 |
Data Required Time | 6.064 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
Launch Clk | sys_clk[F] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 131 | sys_clk_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 7 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/I1 |
3.382 | 1.099 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/F |
3.862 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1 |
4.961 | 1.099 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F |
5.441 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1 |
6.540 | 1.099 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F |
7.020 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I0 |
8.052 | 1.032 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F |
8.532 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | sys_clk | |||
5.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 131 | sys_clk_ibuf/O |
6.464 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK |
6.064 | -0.400 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
Clock Skew: | 0.120 |
Setup Relationship: | 5.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:Slack | -2.468 |
Data Arrival Time | 8.532 |
Data Required Time | 6.064 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
Launch Clk | sys_clk[F] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 131 | sys_clk_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 7 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/I1 |
3.382 | 1.099 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/F |
3.862 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1 |
4.961 | 1.099 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F |
5.441 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1 |
6.540 | 1.099 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F |
7.020 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I0 |
8.052 | 1.032 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F |
8.532 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | sys_clk | |||
5.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 131 | sys_clk_ibuf/O |
6.464 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK |
6.064 | -0.400 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
Clock Skew: | 0.120 |
Setup Relationship: | 5.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:Slack | -2.258 |
Data Arrival Time | 8.322 |
Data Required Time | 6.064 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
Launch Clk | sys_clk[F] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 131 | sys_clk_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 7 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/I1 |
3.382 | 1.099 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/F |
3.862 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1 |
4.961 | 1.099 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F |
5.441 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/I2 |
6.263 | 0.822 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/F |
6.743 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/I1 |
7.842 | 1.099 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/F |
8.322 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | sys_clk | |||
5.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 131 | sys_clk_ibuf/O |
6.464 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
6.064 | -0.400 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
Clock Skew: | 0.120 |
Setup Relationship: | 5.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:Slack | -0.402 |
Data Arrival Time | 6.466 |
Data Required Time | 6.064 |
From | Gowin_EMPU_inst/u_flash_wrap/hready_out_s1 |
To | Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3 |
Launch Clk | sys_clk[F] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 131 | sys_clk_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n95_s1/I1 |
3.382 | 1.099 | tINS | FF | 3 | Gowin_EMPU_inst/u_flash_wrap/n95_s1/F |
3.862 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n77_s1/I2 |
4.684 | 0.822 | tINS | FF | 14 | Gowin_EMPU_inst/u_flash_wrap/n77_s1/F |
5.164 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n157_s0/I2 |
5.986 | 0.822 | tINS | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n157_s0/F |
6.466 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | sys_clk | |||
5.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 131 | sys_clk_ibuf/O |
6.464 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/CLK |
6.064 | -0.400 | tSu | 1 | Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3 |
Clock Skew: | 0.120 |
Setup Relationship: | 5.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 2.743, 53.561%; route: 1.920, 37.490%; tC2Q: 0.458, 8.949% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:Slack | -0.402 |
Data Arrival Time | 6.466 |
Data Required Time | 6.064 |
From | Gowin_EMPU_inst/u_flash_wrap/hready_out_s1 |
To | Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3 |
Launch Clk | sys_clk[F] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 131 | sys_clk_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n95_s1/I1 |
3.382 | 1.099 | tINS | FF | 3 | Gowin_EMPU_inst/u_flash_wrap/n95_s1/F |
3.862 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n77_s1/I2 |
4.684 | 0.822 | tINS | FF | 14 | Gowin_EMPU_inst/u_flash_wrap/n77_s1/F |
5.164 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n156_s0/I2 |
5.986 | 0.822 | tINS | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/n156_s0/F |
6.466 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | sys_clk | |||
5.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 131 | sys_clk_ibuf/O |
6.464 | 0.480 | tNET | FF | 1 | Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/CLK |
6.064 | -0.400 | tSu | 1 | Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3 |
Clock Skew: | 0.120 |
Setup Relationship: | 5.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 2.743, 53.561%; route: 1.920, 37.490%; tC2Q: 0.458, 8.949% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |