In the previous part, we have seen, that the uC has to deliver roughly 200 mA peak with a maximum rise time of 170 mA / ns on his GPIO Pins.
For this example, I want to define a maximum voltage drop of 100 mV.
If the power source is purely resistive, it is quiet easy to calculate a maximum target impedance.
It would be 100 mV / 200 mA = 0,5 Ohm.
A simulation shows the maximum voltage drop of 100 mV for this configuration:
But this is only theoretical as we do not have a pure resistive power source up to 400 Mhz.
The other possibility would be to calculate the allowable inductivity of the power system to restrict the voltage drop to 100 mV. We know the maximum di/dt of 170 mA / ns. This means the maximum tolerable inductivity is L = u / (di/dt) = 588 pH.
A real PDN would have both, real resistivity and inductivity. So if we assume that the minimum reachable inductivity from package and PDN is 300 pH we can find out by simulation what the maximum resistivity would be to reach our goal of 100 mV voltage drop. It can be shown, that the result is 350 mOhm.
The next part will show, how the real board performs.
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