PnR Messages

Report Title PnR Report
Design File D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\impl\gwsynthesis\gowin_empu_hyperram.vg
Physical Constraints File D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\gowin_empu.cst
Timing Constraints File D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\timing.sdc
Version V1.9.8.03
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Fri Mar 25 11:47:15 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.425s, Elapsed time = 0h 0m 0.425s Placement Phase 1: CPU time = 0h 0m 0.092s, Elapsed time = 0h 0m 0.092s Placement Phase 2: CPU time = 0h 0m 0.475s, Elapsed time = 0h 0m 0.475s Placement Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Total Placement: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.188s, Elapsed time = 0h 0m 0.188s Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Routing: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Generate output files: CPU time = 0h 0m 0.775s, Elapsed time = 0h 0m 0.775s
Total Time and Memory Usage CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 175MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1370/4608 29%
    --LUT,ALU,ROM16 1370(1317 LUT, 53 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 1197/3609 33%
    --Logic Register as Latch 39/3456 1%
    --Logic Register as FF 1135/3456 32%
    --I/O Register as Latch 0/153 0%
    --I/O Register as FF 23/153 15%
CLS 1301/2304 56%
I/O Port 33 -
I/O Buf 32 -
    --Input Buf 20 -
    --Output Buf 7 -
    --Inout Buf 5 -
IOLOGIC 8 IDES4
12 OSER4
10 IODELAY
37%
BSRAM 4 SP
40%
DSP 00%
PLL 1/2 50%
DCS 0/4 0%
DQCE 0/12 0%
OSC 0/1 0%
CLKDIV 1/6 16%
DLLDLY 0/6 0%
DHCEN 1/12 8%
EMCU 1/1 100%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 2/10(20%)
bank 1 10/10(100%)
bank 2 9/9(100%)
bank 3 11/24(45%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 5/8(62%)
SECONDARY 2/8(25%)
GCLK_PIN 5/5(100%)
PLL 1/2(50%)
CLKDIV 1/6(16%)
DLLDLY 0/6(0%)

Global Clock Signals:

Signal Global Clock Location
sys_clk_d PRIMARY LEFT RIGHT
nWR_d PRIMARY LEFT RIGHT
hpram_base_clk PRIMARY LEFT RIGHT
user_clk PRIMARY LEFT RIGHT
S_read_enable PRIMARY LEFT
master_hrst SECONDARY -
ddr_rsti SECONDARY -
hpram_memory_clk HCLK TOP[1] BOTTOM[1]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
sys_clk 45/1 Y in IOT13[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 3.3
uart0_rxd 39/1 Y in IOT26[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 3.3
nWR 8/0 Y in IOT4[B] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
nRD 9/0 Y in IOT5[B] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
nCS 10/0 Y in IOT7[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
A[0] 16/3 Y in IOB6[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[1] 15/3 Y in IOB5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[2] 14/3 Y in IOB4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[3] 13/3 Y in IOB4[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[4] 17/3 Y in IOB6[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[5] 18/3 Y in IOB13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[6] 19/3 Y in IOB13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[7] 20/3 Y in IOB16[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[8] 21/3 Y in IOB16[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[9] 22/3 Y in IOB22[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[10] 23/3 Y in IOB22[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
A[11] 27/2 Y in IOR17[B] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
A[12] 28/2 Y in IOR17[A] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
A[13] 29/2 Y in IOR15[B] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
A[14] 30/2 Y in IOR15[A] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
A15 31/2 Y in IOR11[B] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
uart0_txd 32/2 Y out IOR11[A] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
DIR 33/2 Y out IOR9[B] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
nOE 34/2 Y out IOR2[B] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
nRST 35/2 Y out IOR2[A] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
D[0] 40/1 Y io IOT26[B] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
D[1] 41/1 Y io IOT20[A] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
D[2] 42/1 Y io IOT20[B] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
D[3] 43/1 Y io IOT17[A] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
D[4] 47/1 Y io IOT11[B] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
D[5] 48/1 Y io IOT11[A] LVCMOS33 8 UP NA NA OFF FAST NA NA NA 3.3
D[6] 46/1 Y io IOT13[B] LVCMOS33 8 UP NA NA OFF FAST NA NA NA 3.3
D[7] 44/1 Y io IOT17[B] LVCMOS33 8 UP NA NA OFF FAST NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
4/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.2
6/0 - in IOT3[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
7/0 - in IOT3[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
8/0 nWR in IOT4[B] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
9/0 nRD in IOT5[B] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
10/0 nCS in IOT7[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
1/0 - in IOT10[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
2/0 - in IOT10[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
48/1 D[5] out IOT11[A] LVCMOS33 8 UP NA NA OFF FAST NA NA NA 3.3
47/1 D[4] io IOT11[B] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
45/1 sys_clk in IOT13[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 3.3
46/1 D[6] out IOT13[B] LVCMOS33 8 UP NA NA OFF FAST NA NA NA 3.3
43/1 D[3] io IOT17[A] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
44/1 D[7] out IOT17[B] LVCMOS33 8 UP NA NA OFF FAST NA NA NA 3.3
41/1 D[1] io IOT20[A] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
42/1 D[2] io IOT20[B] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
39/1 uart0_rxd in IOT26[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 3.3
40/1 D[0] io IOT26[B] LVCMOS33 8 UP NA NONE OFF FAST NA NA NA 3.3
13/3 A[3] in IOB4[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
14/3 A[2] in IOB4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
15/3 A[1] in IOB5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
16/3 A[0] in IOB6[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
17/3 A[4] in IOB6[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
18/3 A[5] in IOB13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
19/3 A[6] in IOB13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
20/3 A[7] in IOB16[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
21/3 A[8] in IOB16[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
22/3 A[9] in IOB22[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
23/3 A[10] in IOB22[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
35/2 nRST out IOR2[A] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
34/2 nOE out IOR2[B] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
33/2 DIR out IOR9[B] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
32/2 uart0_txd out IOR11[A] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
31/2 A15 in IOR11[B] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
30/2 A[14] in IOR15[A] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
29/2 A[13] in IOR15[B] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
28/2 A[12] in IOR17[A] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5
27/2 A[11] in IOR17[B] LVCMOS25 NA UP NA NONE NA NA NA OFF NA 2.5