Timing Messages

Report Title Timing Analysis Report
Design File D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\impl\gwsynthesis\gowin_empu_hyperram.vg
Physical Constraints File D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\gowin_empu.cst
Timing Constraint File D:\SpengerCloud\AP\ebooks\Projekte\GoWin\Projekte\FPGA\06_GB02A\src\timing.sdc
Version V1.9.8.03
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Fri Mar 25 11:47:15 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 5151
Numbers of Endpoints Analyzed 3130
Numbers of Falling Endpoints 85
Numbers of Setup Violated Endpoints 435
Numbers of Hold Violated Endpoints 3

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
SYS_CLK Base 37.037 27.000 0.000 18.518 sys_clk
u_Gowin_AHB_HyperRAM_Top/S_read_enable Base 20.000 50.000 0.000 10.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
nWR_d Base 20.000 50.000 0.000 10.000 nWR_ibuf/O
u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk Generated 6.289 159.000 0.000 3.145 sys_clk_ibuf/I SYS_CLK u_Gowin_PLLVR/pllvr_inst/CLKOUT
u_Gowin_PLLVR/pllvr_inst/CLKOUTP.default_gen_clk Generated 6.289 159.000 0.000 3.145 sys_clk_ibuf/I SYS_CLK u_Gowin_PLLVR/pllvr_inst/CLKOUTP
u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk Generated 12.579 79.500 0.000 6.289 sys_clk_ibuf/I SYS_CLK u_Gowin_PLLVR/pllvr_inst/CLKOUTD
u_Gowin_PLLVR/pllvr_inst/CLKOUTD3.default_gen_clk Generated 18.868 53.000 0.000 9.434 sys_clk_ibuf/I SYS_CLK u_Gowin_PLLVR/pllvr_inst/CLKOUTD3
u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk Generated 12.579 79.500 0.000 6.289 u_Gowin_PLLVR/pllvr_inst/CLKOUT u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 SYS_CLK 27.000(MHz) 60.697(MHz) 5 TOP
2 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk 79.500(MHz) 137.095(MHz) 5 TOP
3 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk 79.500(MHz) 76.158(MHz) 6 TOP

No timing paths to get frequency of u_Gowin_AHB_HyperRAM_Top/S_read_enable!

No timing paths to get frequency of nWR_d!

No timing paths to get frequency of u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_Gowin_PLLVR/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_Gowin_PLLVR/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
SYS_CLK Setup 0.000 0
SYS_CLK Hold 0.000 0
u_Gowin_AHB_HyperRAM_Top/S_read_enable Setup 0.000 0
u_Gowin_AHB_HyperRAM_Top/S_read_enable Hold 0.000 0
nWR_d Setup 0.000 0
nWR_d Hold 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk Setup 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk Hold 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUTP.default_gen_clk Setup 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUTP.default_gen_clk Hold 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk Setup 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk Hold 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
u_Gowin_PLLVR/pllvr_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk Setup -13.439 64
u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -12.784 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_10_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 12.406
2 -12.399 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_6_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 12.020
3 -11.940 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_4_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 11.561
4 -11.804 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_20_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 11.425
5 -11.630 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_9_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 11.251
6 -11.503 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_14_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 11.124
7 -11.354 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_3_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.976
8 -11.169 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_5_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.790
9 -11.162 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_11_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.783
10 -11.131 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_21_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.752
11 -11.063 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_19_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.684
12 -10.980 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_8_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.602
13 -10.930 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.551
14 -10.859 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[6]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.357
15 -10.859 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_4_G[6]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.357
16 -10.811 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[30]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.309
17 -10.688 u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_7_s0/D SYS_CLK:[R] u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F] 0.371 0.320 10.309
18 -10.682 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_21_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[22]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.180
19 -10.666 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_2_G[6]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.164
20 -10.660 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_7_G[17]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.158
21 -10.660 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_5_G[17]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.158
22 -10.660 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[17]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.158
23 -10.654 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_3_G[30]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.152
24 -10.654 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[30]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.152
25 -10.651 u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[17]_s0/D SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 9.149

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.333 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 0.928
2 -0.031 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.230
3 -0.031 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.230
4 0.212 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.473
5 0.220 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.481
6 0.220 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.481
7 0.543 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.803
8 0.543 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/CALIB u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.803
9 0.556 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/init_calib_s0/CE u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.571
10 0.557 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_done_0_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CE u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.572
11 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/D u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.708
12 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
13 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
14 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
15 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
16 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
17 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
18 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
19 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
20 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
21 0.708 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.708
22 0.708 u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5/Q u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5/D SYS_CLK:[R] SYS_CLK:[R] 0.000 0.000 0.708
23 0.708 u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0/Q u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0/D SYS_CLK:[R] SYS_CLK:[R] 0.000 0.000 0.708
24 0.709 u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.709
25 0.709 u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/D u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.709

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -8.294 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_11_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 7.148
2 -8.294 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_12_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 7.148
3 -7.805 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_13_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 6.659
4 -7.805 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_14_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 6.659
5 -5.992 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_9_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.846
6 -5.992 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_10_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.846
7 -5.679 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_5_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.533
8 -5.679 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_6_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.533
9 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/mask_s1/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
10 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aevent_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
11 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
12 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_1_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
13 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_2_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
14 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_3_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
15 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_4_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
16 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_5_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
17 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_6_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
18 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
19 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_8_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
20 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_9_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
21 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_10_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
22 -5.528 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/maskhold_11_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.383
23 -5.347 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_7_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.202
24 -5.347 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_8_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 4.202
25 -5.018 u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q u_Gowin_AHB_HyperRAM_Top/Aold_2_s0/CLEAR SYS_CLK:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.699 1.771 3.872

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
2 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
3 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
4 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
5 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
6 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
7 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
8 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
9 2.055 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -0.171 2.271
10 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
11 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
12 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
13 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
14 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
15 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
16 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
17 3.286 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R] 0.000 1.060 2.271
18 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
19 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
20 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
21 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
22 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
23 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
24 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271
25 5.186 u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/RESET u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R] u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F] -3.145 -0.185 2.271

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_syn_0_s0
2 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_d2_s0
3 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_15_s1
4 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_14_s1
5 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_12_s1
6 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_2_s1
7 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_4_s3
8 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_1_s3
9 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_0_s3
10 4.961 6.211 1.250 Low Pulse Width u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_3_s3

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -12.784
Data Arrival Time 644.378
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_10_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.694 1.837 tNET FF 1 R6C16[3][B] u_Gowin_AHB_HyperRAM_Top/n511_s33/I1
641.726 1.032 tINS FF 1 R6C16[3][B] u_Gowin_AHB_HyperRAM_Top/n511_s33/F
643.346 1.620 tNET FF 1 R7C16[2][B] u_Gowin_AHB_HyperRAM_Top/n511_s31/I1
644.378 1.032 tINS FF 1 R7C16[2][B] u_Gowin_AHB_HyperRAM_Top/n511_s31/F
644.378 0.000 tNET FF 1 R7C16[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R7C16[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_10_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_10_s0
631.593 -0.400 tSu 1 R7C16[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_10_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.886, 23.264%; route: 9.061, 73.042%; tC2Q: 0.458, 3.695%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path2

Path Summary:

Slack -12.399
Data Arrival Time 643.992
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_6_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
639.829 7.398 tNET FF 1 R17C10[3][A] u_Gowin_AHB_HyperRAM_Top/n515_s30/S0
640.266 0.437 tINS FF 1 R17C10[3][A] u_Gowin_AHB_HyperRAM_Top/n515_s30/O
641.250 0.984 tNET FF 1 R15C8[3][A] u_Gowin_AHB_HyperRAM_Top/n515_s34/I0
642.072 0.822 tINS FF 1 R15C8[3][A] u_Gowin_AHB_HyperRAM_Top/n515_s34/F
642.893 0.821 tNET FF 1 R13C8[0][A] u_Gowin_AHB_HyperRAM_Top/n515_s31/I3
643.992 1.099 tINS FF 1 R13C8[0][A] u_Gowin_AHB_HyperRAM_Top/n515_s31/F
643.992 0.000 tNET FF 1 R13C8[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R13C8[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_6_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_6_s0
631.593 -0.400 tSu 1 R13C8[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_6_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.358, 19.618%; route: 9.204, 76.569%; tC2Q: 0.458, 3.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path3

Path Summary:

Slack -11.940
Data Arrival Time 643.533
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_4_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.531 1.674 tNET FF 1 R13C5[3][A] u_Gowin_AHB_HyperRAM_Top/n517_s33/I1
641.630 1.099 tINS FF 1 R13C5[3][A] u_Gowin_AHB_HyperRAM_Top/n517_s33/F
642.434 0.804 tNET FF 1 R14C4[2][A] u_Gowin_AHB_HyperRAM_Top/n517_s31/I1
643.533 1.099 tINS FF 1 R14C4[2][A] u_Gowin_AHB_HyperRAM_Top/n517_s31/F
643.533 0.000 tNET FF 1 R14C4[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R14C4[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_4_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_4_s0
631.593 -0.400 tSu 1 R14C4[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_4_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.020, 26.122%; route: 8.083, 69.914%; tC2Q: 0.458, 3.964%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path4

Path Summary:

Slack -11.804
Data Arrival Time 643.397
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_20_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.201 1.344 tNET FF 1 R12C13[3][B] u_Gowin_AHB_HyperRAM_Top/n501_s33/I1
640.827 0.626 tINS FF 1 R12C13[3][B] u_Gowin_AHB_HyperRAM_Top/n501_s33/F
642.771 1.944 tNET FF 1 R6C11[0][A] u_Gowin_AHB_HyperRAM_Top/n501_s31/I1
643.397 0.626 tINS FF 1 R6C11[0][A] u_Gowin_AHB_HyperRAM_Top/n501_s31/F
643.397 0.000 tNET FF 1 R6C11[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R6C11[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_20_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_20_s0
631.593 -0.400 tSu 1 R6C11[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_20_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.074, 18.153%; route: 8.893, 77.835%; tC2Q: 0.458, 4.012%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path5

Path Summary:

Slack -11.630
Data Arrival Time 643.223
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_9_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
641.180 2.323 tNET FF 1 R8C5[2][A] u_Gowin_AHB_HyperRAM_Top/n512_s33/I1
641.982 0.802 tINS FR 1 R8C5[2][A] u_Gowin_AHB_HyperRAM_Top/n512_s33/F
642.401 0.419 tNET RR 1 R8C4[2][A] u_Gowin_AHB_HyperRAM_Top/n512_s31/I1
643.223 0.822 tINS RF 1 R8C4[2][A] u_Gowin_AHB_HyperRAM_Top/n512_s31/F
643.223 0.000 tNET FF 1 R8C4[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R8C4[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_9_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_9_s0
631.593 -0.400 tSu 1 R8C4[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_9_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.446, 21.741%; route: 8.347, 74.186%; tC2Q: 0.458, 4.074%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path6

Path Summary:

Slack -11.503
Data Arrival Time 643.096
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_14_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.355 1.497 tNET FF 1 R13C6[3][A] u_Gowin_AHB_HyperRAM_Top/n507_s33/I1
641.177 0.822 tINS FF 1 R13C6[3][A] u_Gowin_AHB_HyperRAM_Top/n507_s33/F
641.997 0.821 tNET FF 1 R13C7[2][B] u_Gowin_AHB_HyperRAM_Top/n507_s31/I1
643.096 1.099 tINS FF 1 R13C7[2][B] u_Gowin_AHB_HyperRAM_Top/n507_s31/F
643.096 0.000 tNET FF 1 R13C7[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R13C7[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_14_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_14_s0
631.593 -0.400 tSu 1 R13C7[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_14_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.743, 24.658%; route: 7.923, 71.222%; tC2Q: 0.458, 4.120%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path7

Path Summary:

Slack -11.354
Data Arrival Time 642.948
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_3_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
641.021 2.164 tNET FF 1 R8C4[3][A] u_Gowin_AHB_HyperRAM_Top/n518_s33/I1
642.120 1.099 tINS FF 1 R8C4[3][A] u_Gowin_AHB_HyperRAM_Top/n518_s33/F
642.126 0.005 tNET FF 1 R8C4[0][A] u_Gowin_AHB_HyperRAM_Top/n518_s31/I1
642.948 0.822 tINS FF 1 R8C4[0][A] u_Gowin_AHB_HyperRAM_Top/n518_s31/F
642.948 0.000 tNET FF 1 R8C4[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R8C4[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_3_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_3_s0
631.593 -0.400 tSu 1 R8C4[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_3_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.743, 24.992%; route: 7.774, 70.832%; tC2Q: 0.458, 4.176%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path8

Path Summary:

Slack -11.169
Data Arrival Time 642.762
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_5_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.686 1.829 tNET FF 1 R7C14[3][A] u_Gowin_AHB_HyperRAM_Top/n516_s33/I1
641.311 0.625 tINS FR 1 R7C14[3][A] u_Gowin_AHB_HyperRAM_Top/n516_s33/F
641.730 0.419 tNET RR 1 R7C13[0][A] u_Gowin_AHB_HyperRAM_Top/n516_s31/I1
642.762 1.032 tINS RF 1 R7C13[0][A] u_Gowin_AHB_HyperRAM_Top/n516_s31/F
642.762 0.000 tNET FF 1 R7C13[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R7C13[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_5_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_5_s0
631.593 -0.400 tSu 1 R7C13[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_5_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.479, 22.975%; route: 7.853, 72.778%; tC2Q: 0.458, 4.248%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path9

Path Summary:

Slack -11.162
Data Arrival Time 642.755
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_11_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
641.025 2.168 tNET FF 1 R6C16[1][B] u_Gowin_AHB_HyperRAM_Top/n510_s33/I1
641.651 0.626 tINS FF 1 R6C16[1][B] u_Gowin_AHB_HyperRAM_Top/n510_s33/F
641.656 0.005 tNET FF 1 R6C16[2][A] u_Gowin_AHB_HyperRAM_Top/n510_s31/I1
642.755 1.099 tINS FF 1 R6C16[2][A] u_Gowin_AHB_HyperRAM_Top/n510_s31/F
642.755 0.000 tNET FF 1 R6C16[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R6C16[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_11_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_11_s0
631.593 -0.400 tSu 1 R6C16[2][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_11_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.547, 23.620%; route: 7.778, 72.129%; tC2Q: 0.458, 4.250%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path10

Path Summary:

Slack -11.131
Data Arrival Time 642.724
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_21_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
639.344 6.914 tNET FF 1 R17C11[3][A] u_Gowin_AHB_HyperRAM_Top/n500_s30/S0
639.816 0.472 tINS FR 1 R17C11[3][A] u_Gowin_AHB_HyperRAM_Top/n500_s30/O
641.075 1.258 tNET RR 1 R9C11[2][A] u_Gowin_AHB_HyperRAM_Top/n500_s34/I0
641.897 0.822 tINS RF 1 R9C11[2][A] u_Gowin_AHB_HyperRAM_Top/n500_s34/F
641.902 0.005 tNET FF 1 R9C11[1][B] u_Gowin_AHB_HyperRAM_Top/n500_s31/I3
642.724 0.822 tINS FF 1 R9C11[1][B] u_Gowin_AHB_HyperRAM_Top/n500_s31/F
642.724 0.000 tNET FF 1 R9C11[1][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R9C11[1][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_21_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_21_s0
631.593 -0.400 tSu 1 R9C11[1][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_21_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.116, 19.680%; route: 8.178, 76.057%; tC2Q: 0.458, 4.263%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path11

Path Summary:

Slack -11.063
Data Arrival Time 642.657
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_19_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.355 1.497 tNET FF 1 R7C9[3][A] u_Gowin_AHB_HyperRAM_Top/n502_s33/I1
641.416 1.061 tINS FR 1 R7C9[3][A] u_Gowin_AHB_HyperRAM_Top/n502_s33/F
641.835 0.419 tNET RR 1 R6C9[2][B] u_Gowin_AHB_HyperRAM_Top/n502_s31/I1
642.657 0.822 tINS RF 1 R6C9[2][B] u_Gowin_AHB_HyperRAM_Top/n502_s31/F
642.657 0.000 tNET FF 1 R6C9[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R6C9[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_19_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_19_s0
631.593 -0.400 tSu 1 R6C9[2][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_19_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.705, 25.317%; route: 7.521, 70.393%; tC2Q: 0.458, 4.290%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path12

Path Summary:

Slack -10.980
Data Arrival Time 642.574
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_8_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.846 6.416 tNET FF 1 R16C10[3][A] u_Gowin_AHB_HyperRAM_Top/n513_s30/S0
639.318 0.472 tINS FR 1 R16C10[3][A] u_Gowin_AHB_HyperRAM_Top/n513_s30/O
640.112 0.793 tNET RR 1 R14C9[2][B] u_Gowin_AHB_HyperRAM_Top/n513_s34/I0
641.144 1.032 tINS RF 1 R14C9[2][B] u_Gowin_AHB_HyperRAM_Top/n513_s34/F
641.948 0.804 tNET FF 1 R13C8[0][B] u_Gowin_AHB_HyperRAM_Top/n513_s31/I3
642.574 0.626 tINS FF 1 R13C8[0][B] u_Gowin_AHB_HyperRAM_Top/n513_s31/F
642.574 0.000 tNET FF 1 R13C8[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R13C8[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_8_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_8_s0
631.593 -0.400 tSu 1 R13C8[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_8_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.130, 20.091%; route: 8.013, 75.586%; tC2Q: 0.458, 4.323%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path13

Path Summary:

Slack -10.930
Data Arrival Time 642.523
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
635.585 3.155 tNET FF 1 R8C14[3][B] u_Gowin_AHB_HyperRAM_Top/n500_s35/I0
636.211 0.626 tINS FF 21 R8C14[3][B] u_Gowin_AHB_HyperRAM_Top/n500_s35/F
637.417 1.206 tNET FF 1 R12C13[1][B] u_Gowin_AHB_HyperRAM_Top/n503_s34/I3
638.449 1.032 tINS FF 1 R12C13[1][B] u_Gowin_AHB_HyperRAM_Top/n503_s34/F
640.387 1.938 tNET FF 1 R9C8[3][B] u_Gowin_AHB_HyperRAM_Top/n503_s32/I3
641.486 1.099 tINS FF 1 R9C8[3][B] u_Gowin_AHB_HyperRAM_Top/n503_s32/F
641.491 0.005 tNET FF 1 R9C8[1][A] u_Gowin_AHB_HyperRAM_Top/n503_s31/I3
642.523 1.032 tINS FF 1 R9C8[1][A] u_Gowin_AHB_HyperRAM_Top/n503_s31/F
642.523 0.000 tNET FF 1 R9C8[1][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R9C8[1][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0
631.593 -0.400 tSu 1 R9C8[1][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_18_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.789, 35.911%; route: 6.304, 59.745%; tC2Q: 0.458, 4.344%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path14

Path Summary:

Slack -10.859
Data Arrival Time 48.737
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[6]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R9C9[2][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/CLK
39.838 0.458 tC2Q RR 2 R9C9[2][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/Q
40.261 0.422 tNET RR 1 R8C9[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_17_s8/I0
41.322 1.061 tINS RR 1 R8C9[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_17_s8/F
41.741 0.419 tNET RR 1 R8C10[2][A] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_17_s1/I1
42.773 1.032 tINS RF 1 R8C10[2][A] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_17_s1/F
44.711 1.938 tNET FF 1 R8C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_17_s0/I1
45.810 1.099 tINS FF 8 R8C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_17_s0/F
48.737 2.927 tNET FF 1 R16C31[0][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[6]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C31[0][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[6]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[6]_s0
37.878 -0.400 tSu 1 R16C31[0][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[6]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.192, 34.114%; route: 5.707, 60.988%; tC2Q: 0.458, 4.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack -10.859
Data Arrival Time 48.737
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_4_G[6]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R9C9[2][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/CLK
39.838 0.458 tC2Q RR 2 R9C9[2][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/Q
40.261 0.422 tNET RR 1 R8C9[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_17_s8/I0
41.322 1.061 tINS RR 1 R8C9[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_17_s8/F
41.741 0.419 tNET RR 1 R8C10[2][A] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_17_s1/I1
42.773 1.032 tINS RF 1 R8C10[2][A] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_17_s1/F
44.711 1.938 tNET FF 1 R8C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_17_s0/I1
45.810 1.099 tINS FF 8 R8C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_17_s0/F
48.737 2.927 tNET FF 1 R16C31[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_4_G[6]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C31[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_4_G[6]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_4_G[6]_s0
37.878 -0.400 tSu 1 R16C31[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_4_G[6]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.192, 34.114%; route: 5.707, 60.988%; tC2Q: 0.458, 4.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack -10.811
Data Arrival Time 48.689
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[30]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C10[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/CLK
39.838 0.458 tC2Q RR 2 R6C10[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/Q
40.261 0.422 tNET RR 1 R6C10[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_23_s9/I0
41.360 1.099 tINS RF 1 R6C10[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_23_s9/F
41.696 0.336 tNET FF 1 R6C10[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_23_s1/I2
42.728 1.032 tINS FF 1 R6C10[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_23_s1/F
44.831 2.103 tNET FF 1 R8C23[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_23_s0/I1
45.930 1.099 tINS FF 8 R8C23[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_23_s0/F
48.689 2.760 tNET FF 1 R8C36[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[30]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R8C36[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[30]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[30]_s0
37.878 -0.400 tSu 1 R8C36[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[30]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.230, 34.697%; route: 5.621, 60.380%; tC2Q: 0.458, 4.923%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack -10.688
Data Arrival Time 642.281
Data Required Time 631.593
From u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0
To u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_7_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_Gowin_AHB_HyperRAM_Top/S_read_enable:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
629.629 629.629 active clock edge time
629.629 0.000 SYS_CLK
629.629 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
630.611 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
631.972 1.361 tNET RR 1 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/CLK
632.430 0.458 tC2Q RF 77 R15C2[0][B] u_Gowin_AHB_HyperRAM_Top/S_ahb_address_3_s0/Q
638.035 5.605 tNET FF 1 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/I1
638.857 0.822 tINS FF 16 R14C11[3][B] u_Gowin_AHB_HyperRAM_Top/n238_s3/F
640.355 1.497 tNET FF 1 R15C6[0][B] u_Gowin_AHB_HyperRAM_Top/n514_s33/I1
641.177 0.822 tINS FF 1 R15C6[0][B] u_Gowin_AHB_HyperRAM_Top/n514_s33/F
641.182 0.005 tNET FF 1 R15C6[0][A] u_Gowin_AHB_HyperRAM_Top/n514_s31/I1
642.281 1.099 tINS FF 1 R15C6[0][A] u_Gowin_AHB_HyperRAM_Top/n514_s31/F
642.281 0.000 tNET FF 1 R15C6[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
630.000 630.000 active clock edge time
630.000 0.000 u_Gowin_AHB_HyperRAM_Top/S_read_enable
630.000 0.000 tCL FF 32 R7C7[0][B] u_Gowin_AHB_HyperRAM_Top/S_read_enable_s0/Q
632.023 2.023 tNET FF 1 R15C6[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_7_s0/G
631.993 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_7_s0
631.593 -0.400 tSu 1 R15C6[0][A] u_Gowin_AHB_HyperRAM_Top/S_ahb_rdata_7_s0

Path Statistics:

Clock Skew -0.320
Setup Relationship 0.371
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.743, 26.608%; route: 7.108, 68.946%; tC2Q: 0.458, 4.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.023, 100.000%

Path18

Path Summary:

Slack -10.682
Data Arrival Time 48.560
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_21_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[22]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C11[2][B] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_21_s0/CLK
39.838 0.458 tC2Q RF 2 R11C11[2][B] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_21_s0/Q
40.183 0.345 tNET FF 1 R11C11[3][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_21_s9/I0
41.244 1.061 tINS FR 1 R11C11[3][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_21_s9/F
41.663 0.419 tNET RR 1 R11C12[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_21_s1/I2
42.762 1.099 tINS RF 1 R11C12[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_21_s1/F
44.216 1.453 tNET FF 1 R9C21[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_21_s0/I1
45.315 1.099 tINS FF 8 R9C21[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_21_s0/F
48.560 3.246 tNET FF 1 R7C35[2][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[22]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R7C35[2][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[22]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[22]_s0
37.878 -0.400 tSu 1 R7C35[2][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_6_G[22]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.259, 35.500%; route: 5.463, 59.507%; tC2Q: 0.458, 4.993%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack -10.666
Data Arrival Time 48.544
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_2_G[6]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R9C9[2][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/CLK
39.838 0.458 tC2Q RR 2 R9C9[2][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in0_17_s0/Q
40.261 0.422 tNET RR 1 R8C9[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_17_s8/I0
41.322 1.061 tINS RR 1 R8C9[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_17_s8/F
41.741 0.419 tNET RR 1 R8C10[2][A] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_17_s1/I1
42.773 1.032 tINS RF 1 R8C10[2][A] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_17_s1/F
44.711 1.938 tNET FF 1 R8C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_17_s0/I1
45.810 1.099 tINS FF 8 R8C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_17_s0/F
48.544 2.734 tNET FF 1 R16C31[2][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_2_G[6]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C31[2][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_2_G[6]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_2_G[6]_s0
37.878 -0.400 tSu 1 R16C31[2][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_2_G[6]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.192, 34.833%; route: 5.513, 60.166%; tC2Q: 0.458, 5.002%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack -10.660
Data Arrival Time 48.538
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_7_G[17]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/CLK
39.838 0.458 tC2Q RR 2 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q
40.259 0.420 tNET RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/I1
41.285 1.026 tINS RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/F
41.703 0.419 tNET RR 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/I1
42.329 0.626 tINS RF 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/F
44.432 2.103 tNET FF 1 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/I1
45.464 1.032 tINS FF 8 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/F
48.538 3.074 tNET FF 1 R16C32[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_7_G[17]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C32[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_7_G[17]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_7_G[17]_s0
37.878 -0.400 tSu 1 R16C32[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_7_G[17]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.684, 29.307%; route: 6.016, 65.688%; tC2Q: 0.458, 5.005%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack -10.660
Data Arrival Time 48.538
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_5_G[17]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/CLK
39.838 0.458 tC2Q RR 2 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q
40.259 0.420 tNET RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/I1
41.285 1.026 tINS RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/F
41.703 0.419 tNET RR 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/I1
42.329 0.626 tINS RF 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/F
44.432 2.103 tNET FF 1 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/I1
45.464 1.032 tINS FF 8 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/F
48.538 3.074 tNET FF 1 R16C32[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_5_G[17]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C32[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_5_G[17]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_5_G[17]_s0
37.878 -0.400 tSu 1 R16C32[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_5_G[17]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.684, 29.307%; route: 6.016, 65.688%; tC2Q: 0.458, 5.005%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack -10.660
Data Arrival Time 48.538
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[17]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/CLK
39.838 0.458 tC2Q RR 2 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q
40.259 0.420 tNET RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/I1
41.285 1.026 tINS RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/F
41.703 0.419 tNET RR 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/I1
42.329 0.626 tINS RF 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/F
44.432 2.103 tNET FF 1 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/I1
45.464 1.032 tINS FF 8 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/F
48.538 3.074 tNET FF 1 R16C32[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[17]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C32[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[17]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[17]_s0
37.878 -0.400 tSu 1 R16C32[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[17]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.684, 29.307%; route: 6.016, 65.688%; tC2Q: 0.458, 5.005%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack -10.654
Data Arrival Time 48.532
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_3_G[30]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C10[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/CLK
39.838 0.458 tC2Q RR 2 R6C10[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/Q
40.261 0.422 tNET RR 1 R6C10[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_23_s9/I0
41.360 1.099 tINS RF 1 R6C10[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_23_s9/F
41.696 0.336 tNET FF 1 R6C10[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_23_s1/I2
42.728 1.032 tINS FF 1 R6C10[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_23_s1/F
44.831 2.103 tNET FF 1 R8C23[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_23_s0/I1
45.930 1.099 tINS FF 8 R8C23[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_23_s0/F
48.532 2.602 tNET FF 1 R6C33[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_3_G[30]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R6C33[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_3_G[30]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_3_G[30]_s0
37.878 -0.400 tSu 1 R6C33[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_3_G[30]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.230, 35.294%; route: 5.463, 59.697%; tC2Q: 0.458, 5.008%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack -10.654
Data Arrival Time 48.532
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[30]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C10[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/CLK
39.838 0.458 tC2Q RR 2 R6C10[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in2_23_s0/Q
40.261 0.422 tNET RR 1 R6C10[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_23_s9/I0
41.360 1.099 tINS RF 1 R6C10[1][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_23_s9/F
41.696 0.336 tNET FF 1 R6C10[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_23_s1/I2
42.728 1.032 tINS FF 1 R6C10[2][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_23_s1/F
44.831 2.103 tNET FF 1 R8C23[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_23_s0/I1
45.930 1.099 tINS FF 8 R8C23[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_23_s0/F
48.532 2.602 tNET FF 1 R6C33[0][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[30]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R6C33[0][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[30]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[30]_s0
37.878 -0.400 tSu 1 R6C33[0][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_1_G[30]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 3.230, 35.294%; route: 5.463, 59.697%; tC2Q: 0.458, 5.008%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack -10.651
Data Arrival Time 48.529
Data Required Time 37.878
From u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[17]_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/CLK
39.838 0.458 tC2Q RR 2 R6C6[1][A] u_Gowin_AHB_HyperRAM_Top/S_reg_data_in1_12_s0/Q
40.259 0.420 tNET RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/I1
41.285 1.026 tINS RR 1 R6C6[0][B] u_Gowin_AHB_HyperRAM_Top/S_hpram_wrdata_12_s8/F
41.703 0.419 tNET RR 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/I1
42.329 0.626 tINS RF 1 R6C7[0][B] u_Gowin_AHB_HyperRAM_Top/W_HPRAM_WRDATA_12_s1/F
44.432 2.103 tNET FF 1 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/I1
45.464 1.032 tINS FF 8 R7C21[1][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/wr_data_d_12_s0/F
48.529 3.065 tNET FF 1 R14C32[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[17]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R14C32[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[17]_s0/CLK
38.278 -0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[17]_s0
37.878 -0.400 tSu 1 R14C32[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_RAMREG_0_G[17]_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.684, 29.336%; route: 6.007, 65.654%; tC2Q: 0.458, 5.010%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.333
Data Arrival Time 1.441
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RR 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.441 0.594 tNET RR 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
1.774 0.000 tHld 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.594, 64.072%; tC2Q: 0.333, 35.928%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path2

Path Summary:

Slack -0.031
Data Arrival Time 1.743
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RF 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.743 0.896 tNET FF 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
1.774 0.000 tHld 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.896, 72.893%; tC2Q: 0.333, 27.107%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path3

Path Summary:

Slack -0.031
Data Arrival Time 1.743
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RF 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.743 0.896 tNET FF 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
1.774 0.000 tHld 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.896, 72.893%; tC2Q: 0.333, 27.107%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path4

Path Summary:

Slack 0.212
Data Arrival Time 1.986
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RR 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.986 1.140 tNET RR 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
1.774 0.000 tHld 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.140, 77.369%; tC2Q: 0.333, 22.631%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path5

Path Summary:

Slack 0.220
Data Arrival Time 1.994
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RR 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.994 1.148 tNET RR 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
1.774 0.000 tHld 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.148, 77.492%; tC2Q: 0.333, 22.508%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path6

Path Summary:

Slack 0.220
Data Arrival Time 1.994
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RR 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.994 1.148 tNET RR 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
1.774 0.000 tHld 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.148, 77.492%; tC2Q: 0.333, 22.508%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path7

Path Summary:

Slack 0.543
Data Arrival Time 2.316
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RR 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.316 1.470 tNET RR 1 IOB7[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB7[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
1.774 0.000 tHld 1 IOB7[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.470, 81.514%; tC2Q: 0.333, 18.486%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path8

Path Summary:

Slack 0.543
Data Arrival Time 2.316
Data Required Time 1.774
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846 0.333 tC2Q RR 11 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.316 1.470 tNET RR 1 IOB7[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB7[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4
1.774 0.000 tHld 1 IOB7[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.470, 81.514%; tC2Q: 0.333, 18.486%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path9

Path Summary:

Slack 0.556
Data Arrival Time 1.084
Data Required Time 0.528
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/init_calib_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.846 0.333 tC2Q RR 2 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/Q
1.084 0.238 tNET RR 1 R16C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/init_calib_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R16C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/init_calib_s0/CLK
0.528 0.015 tHld 1 R16C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/init_calib_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack 0.557
Data Arrival Time 1.085
Data Required Time 0.528
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_done_0_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_done_0_s0/CLK
0.846 0.333 tC2Q RR 4 R11C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_done_0_s0/Q
1.085 0.239 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.528 0.015 tHld 1 R11C24[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/calib_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack 0.708
Data Arrival Time 2.280
Data Required Time 1.573
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLK
1.906 0.333 tC2Q RR 3 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/Q
1.908 0.002 tNET RR 1 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/n44_s1/I2
2.280 0.372 tINS RF 1 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/n44_s1/F
2.280 0.000 tNET FF 1 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLK
1.573 0.000 tHld 1 R6C19[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path12

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3/CLK
0.846 0.333 tC2Q RR 4 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3/Q
0.849 0.002 tNET RR 1 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n877_s3/I2
1.221 0.372 tINS RF 1 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n877_s3/F
1.221 0.000 tNET FF 1 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3/CLK
0.513 0.000 tHld 1 R6C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_1_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3/CLK
0.846 0.333 tC2Q RR 2 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3/Q
0.849 0.002 tNET RR 1 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n875_s4/I2
1.221 0.372 tINS RF 1 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n875_s4/F
1.221 0.000 tNET FF 1 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3/CLK
0.513 0.000 tHld 1 R4C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_3_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1/CLK
0.846 0.333 tC2Q RR 4 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1/Q
0.849 0.002 tNET RR 1 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n1093_s3/I1
1.221 0.372 tINS RF 1 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n1093_s3/F
1.221 0.000 tNET FF 1 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1/CLK
0.513 0.000 tHld 1 R13C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].check_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1/CLK
0.846 0.333 tC2Q RR 3 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1/Q
0.849 0.002 tNET RR 1 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n876_s1/I3
1.221 0.372 tINS RF 1 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n876_s1/F
1.221 0.000 tNET FF 1 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1/CLK
0.513 0.000 tHld 1 R6C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/timer_cnt1_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1/CLK
0.846 0.333 tC2Q RR 3 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1/Q
0.849 0.002 tNET RR 1 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n183_s1/I3
1.221 0.372 tINS RF 1 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n183_s1/F
1.221 0.000 tNET FF 1 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1/CLK
0.513 0.000 tHld 1 R9C21[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1/CLK
0.846 0.333 tC2Q RR 2 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1/Q
0.849 0.002 tNET RR 1 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n178_s1/I3
1.221 0.372 tINS RF 1 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n178_s1/F
1.221 0.000 tNET FF 1 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1/CLK
0.513 0.000 tHld 1 R8C22[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/tvcs_cnt_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0/CLK
0.846 0.333 tC2Q RR 3 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0/Q
0.849 0.002 tNET RR 1 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n958_s1/I1
1.221 0.372 tINS RF 1 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n958_s1/F
1.221 0.000 tNET FF 1 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0/CLK
0.513 0.000 tHld 1 R3C23[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0/CLK
0.846 0.333 tC2Q RR 2 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0/Q
0.849 0.002 tNET RR 1 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n957_s1/I2
1.221 0.372 tINS RF 1 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n957_s1/F
1.221 0.000 tNET FF 1 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0/CLK
0.513 0.000 tHld 1 R3C23[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/read_calibration[0].add_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.846 0.333 tC2Q RR 2 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/Q
0.849 0.002 tNET RR 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n_state.INIT_CALIB_DONE_s15/I1
1.221 0.372 tINS RF 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/n_state.INIT_CALIB_DONE_s15/F
1.221 0.000 tNET FF 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.513 0.000 tHld 1 R16C24[0][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack 0.708
Data Arrival Time 1.221
Data Required Time 0.513
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1/CLK
0.846 0.333 tC2Q RR 145 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1/Q
0.849 0.002 tNET RR 1 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/n172_s1/I2
1.221 0.372 tINS RF 1 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/n172_s1/F
1.221 0.000 tNET FF 1 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1/CLK
0.513 0.000 tHld 1 R9C32[1][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path22

Path Summary:

Slack 0.708
Data Arrival Time 2.518
Data Required Time 1.811
From u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5
To u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5
Launch Clk SYS_CLK:[R]
Latch Clk SYS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYS_CLK
0.000 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
0.844 0.844 tINS RR 310 IOT13[A] sys_clk_ibuf/O
1.811 0.966 tNET RR 1 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5/CLK
2.144 0.333 tC2Q RR 2 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5/Q
2.146 0.002 tNET RR 1 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n225_s7/I1
2.518 0.372 tINS RF 1 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n225_s7/F
2.518 0.000 tNET FF 1 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYS_CLK
0.000 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
0.844 0.844 tINS RR 310 IOT13[A] sys_clk_ibuf/O
1.811 0.966 tNET RR 1 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5/CLK
1.811 0.000 tHld 1 R5C16[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/read_wait_done_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path23

Path Summary:

Slack 0.708
Data Arrival Time 2.518
Data Required Time 1.811
From u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0
To u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0
Launch Clk SYS_CLK:[R]
Latch Clk SYS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYS_CLK
0.000 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
0.844 0.844 tINS RR 310 IOT13[A] sys_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0/CLK
2.144 0.333 tC2Q RR 2 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0/Q
2.146 0.002 tNET RR 1 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/n214_s1/I0
2.518 0.372 tINS RF 1 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/n214_s1/F
2.518 0.000 tNET FF 1 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYS_CLK
0.000 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
0.844 0.844 tINS RR 310 IOT13[A] sys_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0/CLK
1.811 0.000 tHld 1 R4C6[0][A] u_Gowin_EMPU_Top/Gowin_EMPU_inst/u_flash_wrap/se_out_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path24

Path Summary:

Slack 0.709
Data Arrival Time 1.222
Data Required Time 0.513
From u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/CLK
0.846 0.333 tC2Q RR 7 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/Q
0.850 0.004 tNET RR 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/n1328_s1/I0
1.222 0.372 tINS RF 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/n1328_s1/F
1.222 0.000 tNET FF 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/CLK
0.513 0.000 tHld 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path25

Path Summary:

Slack 0.709
Data Arrival Time 1.222
Data Required Time 0.513
From u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0
Launch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/CLK
0.846 0.333 tC2Q RR 7 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/Q
0.850 0.004 tNET RR 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/n1321_s1/I3
1.222 0.372 tINS RF 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/n1321_s1/F
1.222 0.000 tNET FF 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/CLK
0.513 0.000 tHld 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -8.294
Data Arrival Time 46.529
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_11_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
46.529 5.083 tNET FF 1 IOR17[B] u_Gowin_AHB_HyperRAM_Top/Aold_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOR17[B] u_Gowin_AHB_HyperRAM_Top/Aold_11_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_11_s0
38.235 -0.043 tSu 1 IOR17[B] u_Gowin_AHB_HyperRAM_Top/Aold_11_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 8.757%; route: 6.064, 84.831%; tC2Q: 0.458, 6.412%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack -8.294
Data Arrival Time 46.529
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_12_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
46.529 5.083 tNET FF 1 IOR17[A] u_Gowin_AHB_HyperRAM_Top/Aold_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOR17[A] u_Gowin_AHB_HyperRAM_Top/Aold_12_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_12_s0
38.235 -0.043 tSu 1 IOR17[A] u_Gowin_AHB_HyperRAM_Top/Aold_12_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 8.757%; route: 6.064, 84.831%; tC2Q: 0.458, 6.412%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack -7.805
Data Arrival Time 46.039
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_13_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
46.039 4.594 tNET FF 1 IOR15[B] u_Gowin_AHB_HyperRAM_Top/Aold_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOR15[B] u_Gowin_AHB_HyperRAM_Top/Aold_13_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_13_s0
38.235 -0.043 tSu 1 IOR15[B] u_Gowin_AHB_HyperRAM_Top/Aold_13_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 9.400%; route: 5.575, 83.717%; tC2Q: 0.458, 6.883%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack -7.805
Data Arrival Time 46.039
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_14_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
46.039 4.594 tNET FF 1 IOR15[A] u_Gowin_AHB_HyperRAM_Top/Aold_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOR15[A] u_Gowin_AHB_HyperRAM_Top/Aold_14_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_14_s0
38.235 -0.043 tSu 1 IOR15[A] u_Gowin_AHB_HyperRAM_Top/Aold_14_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 9.400%; route: 5.575, 83.717%; tC2Q: 0.458, 6.883%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack -5.992
Data Arrival Time 44.227
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_9_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
44.227 2.781 tNET FF 1 IOB22[A] u_Gowin_AHB_HyperRAM_Top/Aold_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB22[A] u_Gowin_AHB_HyperRAM_Top/Aold_9_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_9_s0
38.235 -0.043 tSu 1 IOB22[A] u_Gowin_AHB_HyperRAM_Top/Aold_9_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 12.917%; route: 3.762, 77.626%; tC2Q: 0.458, 9.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack -5.992
Data Arrival Time 44.227
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_10_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
44.227 2.781 tNET FF 1 IOB22[B] u_Gowin_AHB_HyperRAM_Top/Aold_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB22[B] u_Gowin_AHB_HyperRAM_Top/Aold_10_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_10_s0
38.235 -0.043 tSu 1 IOB22[B] u_Gowin_AHB_HyperRAM_Top/Aold_10_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 12.917%; route: 3.762, 77.626%; tC2Q: 0.458, 9.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack -5.679
Data Arrival Time 43.914
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_5_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.914 2.468 tNET FF 1 IOB13[A] u_Gowin_AHB_HyperRAM_Top/Aold_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB13[A] u_Gowin_AHB_HyperRAM_Top/Aold_5_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_5_s0
38.235 -0.043 tSu 1 IOB13[A] u_Gowin_AHB_HyperRAM_Top/Aold_5_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 13.809%; route: 3.449, 76.081%; tC2Q: 0.458, 10.110%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack -5.679
Data Arrival Time 43.914
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_6_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.914 2.468 tNET FF 1 IOB13[B] u_Gowin_AHB_HyperRAM_Top/Aold_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB13[B] u_Gowin_AHB_HyperRAM_Top/Aold_6_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_6_s0
38.235 -0.043 tSu 1 IOB13[B] u_Gowin_AHB_HyperRAM_Top/Aold_6_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 13.809%; route: 3.449, 76.081%; tC2Q: 0.458, 10.110%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/mask_s1
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R15C18[1][A] u_Gowin_AHB_HyperRAM_Top/mask_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R15C18[1][A] u_Gowin_AHB_HyperRAM_Top/mask_s1/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/mask_s1
38.235 -0.043 tSu 1 R15C18[1][A] u_Gowin_AHB_HyperRAM_Top/mask_s1

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aevent_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R17C17[2][B] u_Gowin_AHB_HyperRAM_Top/Aevent_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R17C17[2][B] u_Gowin_AHB_HyperRAM_Top/Aevent_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aevent_s0
38.235 -0.043 tSu 1 R17C17[2][B] u_Gowin_AHB_HyperRAM_Top/Aevent_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0
38.235 -0.043 tSu 1 R18C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_0_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_1_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R17C17[1][B] u_Gowin_AHB_HyperRAM_Top/maskhold_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R17C17[1][B] u_Gowin_AHB_HyperRAM_Top/maskhold_1_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_1_s0
38.235 -0.043 tSu 1 R17C17[1][B] u_Gowin_AHB_HyperRAM_Top/maskhold_1_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_2_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R17C17[2][A] u_Gowin_AHB_HyperRAM_Top/maskhold_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R17C17[2][A] u_Gowin_AHB_HyperRAM_Top/maskhold_2_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_2_s0
38.235 -0.043 tSu 1 R17C17[2][A] u_Gowin_AHB_HyperRAM_Top/maskhold_2_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_3_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R17C17[0][B] u_Gowin_AHB_HyperRAM_Top/maskhold_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R17C17[0][B] u_Gowin_AHB_HyperRAM_Top/maskhold_3_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_3_s0
38.235 -0.043 tSu 1 R17C17[0][B] u_Gowin_AHB_HyperRAM_Top/maskhold_3_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_4_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R18C16[2][B] u_Gowin_AHB_HyperRAM_Top/maskhold_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R18C16[2][B] u_Gowin_AHB_HyperRAM_Top/maskhold_4_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_4_s0
38.235 -0.043 tSu 1 R18C16[2][B] u_Gowin_AHB_HyperRAM_Top/maskhold_4_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_5_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R18C16[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R18C16[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_5_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_5_s0
38.235 -0.043 tSu 1 R18C16[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_5_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_6_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R16C17[2][A] u_Gowin_AHB_HyperRAM_Top/maskhold_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C17[2][A] u_Gowin_AHB_HyperRAM_Top/maskhold_6_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_6_s0
38.235 -0.043 tSu 1 R16C17[2][A] u_Gowin_AHB_HyperRAM_Top/maskhold_6_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0
38.235 -0.043 tSu 1 R17C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_7_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_8_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R17C17[1][A] u_Gowin_AHB_HyperRAM_Top/maskhold_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R17C17[1][A] u_Gowin_AHB_HyperRAM_Top/maskhold_8_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_8_s0
38.235 -0.043 tSu 1 R17C17[1][A] u_Gowin_AHB_HyperRAM_Top/maskhold_8_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_9_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R16C17[2][B] u_Gowin_AHB_HyperRAM_Top/maskhold_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C17[2][B] u_Gowin_AHB_HyperRAM_Top/maskhold_9_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_9_s0
38.235 -0.043 tSu 1 R16C17[2][B] u_Gowin_AHB_HyperRAM_Top/maskhold_9_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_10_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R16C17[1][B] u_Gowin_AHB_HyperRAM_Top/maskhold_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C17[1][B] u_Gowin_AHB_HyperRAM_Top/maskhold_10_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_10_s0
38.235 -0.043 tSu 1 R16C17[1][B] u_Gowin_AHB_HyperRAM_Top/maskhold_10_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack -5.528
Data Arrival Time 43.763
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/maskhold_11_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.763 2.317 tNET FF 1 R16C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 R16C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_11_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/maskhold_11_s0
38.235 -0.043 tSu 1 R16C17[0][A] u_Gowin_AHB_HyperRAM_Top/maskhold_11_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.283%; route: 3.299, 75.260%; tC2Q: 0.458, 10.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack -5.347
Data Arrival Time 43.582
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_7_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.582 2.136 tNET FF 1 IOB16[A] u_Gowin_AHB_HyperRAM_Top/Aold_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB16[A] u_Gowin_AHB_HyperRAM_Top/Aold_7_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_7_s0
38.235 -0.043 tSu 1 IOB16[A] u_Gowin_AHB_HyperRAM_Top/Aold_7_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.898%; route: 3.118, 74.194%; tC2Q: 0.458, 10.908%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack -5.347
Data Arrival Time 43.582
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_8_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.582 2.136 tNET FF 1 IOB16[B] u_Gowin_AHB_HyperRAM_Top/Aold_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB16[B] u_Gowin_AHB_HyperRAM_Top/Aold_8_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_8_s0
38.235 -0.043 tSu 1 IOB16[B] u_Gowin_AHB_HyperRAM_Top/Aold_8_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 14.898%; route: 3.118, 74.194%; tC2Q: 0.458, 10.908%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack -5.018
Data Arrival Time 43.252
Data Required Time 38.235
From u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0
To u_Gowin_AHB_HyperRAM_Top/Aold_2_s0
Launch Clk SYS_CLK:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 SYS_CLK
37.037 0.000 tCL RR 1 IOT13[A] sys_clk_ibuf/I
38.019 0.982 tINS RR 310 IOT13[A] sys_clk_ibuf/O
39.380 1.361 tNET RR 1 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/CLK
39.838 0.458 tC2Q RF 3 R13C4[1][A] u_Gowin_AHB_HyperRAM_Top/S_GB_RESET_s0/Q
40.820 0.981 tNET FF 1 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/I1
41.446 0.626 tINS FF 36 R11C6[1][B] u_Gowin_AHB_HyperRAM_Top/n1303_s0/F
43.252 1.806 tNET FF 1 IOB4[B] u_Gowin_AHB_HyperRAM_Top/Aold_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
38.308 0.242 tNET RR 1 IOB4[B] u_Gowin_AHB_HyperRAM_Top/Aold_2_s0/CLK
38.278 -0.030 tUnc u_Gowin_AHB_HyperRAM_Top/Aold_2_s0
38.235 -0.043 tSu 1 IOB4[B] u_Gowin_AHB_HyperRAM_Top/Aold_2_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.626, 16.167%; route: 2.788, 71.996%; tC2Q: 0.458, 11.837%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 2 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen
1.789 0.015 tHld 1 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path2

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 2 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen
1.789 0.015 tHld 1 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path3

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
1.789 0.015 tHld 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path4

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
1.789 0.015 tHld 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path5

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
1.789 0.015 tHld 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path6

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
1.789 0.015 tHld 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path7

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
1.789 0.015 tHld 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path8

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
1.789 0.015 tHld 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path9

Path Summary:

Slack 2.055
Data Arrival Time 3.844
Data Required Time 1.789
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB7[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB7[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/FCLK
1.774 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
1.789 0.015 tHld 1 IOB7[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew 0.171
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path10

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 2 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen
0.558 0.015 tHld 1 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 2 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen
0.558 0.015 tHld 1 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
0.558 0.015 tHld 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
0.558 0.015 tHld 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
0.558 0.015 tHld 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
0.558 0.015 tHld 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
0.558 0.015 tHld 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack 3.286
Data Arrival Time 3.844
Data Required Time 0.558
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 843 BOTTOMSIDE[1] u_HyperRAM_Memory_Interface_Top/u_hpram_top/clkdiv_s0/CLKOUT
0.513 0.183 tNET RR 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/PCLK
0.543 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
0.558 0.015 tHld 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew -1.060
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 2 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen
-1.342 0.015 tHld 1 IOB15[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path19

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 2 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen
-1.342 0.015 tHld 1 IOB23[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path20

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
-1.342 0.015 tHld 1 IOB29[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path21

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
-1.342 0.015 tHld 1 IOB25[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path22

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
-1.342 0.015 tHld 1 IOB25[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path23

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
-1.342 0.015 tHld 1 IOB24[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path24

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
-1.342 0.015 tHld 1 IOB14[B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Path25

Path Summary:

Slack 5.186
Data Arrival Time 3.844
Data Required Time -1.342
From u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0
To u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
Launch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
1.388 1.388 tCL RR 31 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUTD
1.573 0.185 tNET RR 1 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
1.906 0.333 tC2Q RR 8 R6C19[2][A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/cs_memsync_3_s0/Q
2.178 0.272 tNET RR 1 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/I0
2.563 0.385 tINS RR 378 R8C19[3][B] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/ddr_rsti_s0/F
3.844 1.281 tNET RR 4 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
-3.145 -3.145 active clock edge time
-3.145 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUT.default_gen_clk
-1.698 1.446 tCL FF 1 PLL_L u_Gowin_PLLVR/pllvr_inst/CLKOUT
-1.698 0.000 tNET FF 3 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKIN
-1.477 0.221 tINS FF 22 - u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_dqce_clk_x2p/CLKOUT
-1.387 0.090 tNET FF 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/FCLK
-1.357 0.030 tUnc u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
-1.342 0.015 tHld 1 IOB14[A] u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew 0.185
Hold Relationship -3.145
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.385, 16.952%; route: 1.553, 68.371%; tC2Q: 0.333, 14.677%
Required Clock Path Delay cell: 0.221, 70.966%; route: 0.090, 29.034%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_syn_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_syn_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_syn_0_s0/CLK

MPW2

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_d2_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_d2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_d2_s0/CLK

MPW3

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_15_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_15_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_15_s1/CLK

MPW4

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_14_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_14_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_14_s1/CLK

MPW5

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_12_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_12_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_12_s1/CLK

MPW6

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_2_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_2_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_2_s1/CLK

MPW7

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_4_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_4_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_4_s3/CLK

MPW8

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_1_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK

MPW9

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_0_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_0_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_0_s3/CLK

MPW10

MPW Summary:

Slack: 4.961
Actual Width: 6.211
Required Width: 1.250
Type: Low Pulse Width
Clock: u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
Objects: u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_3_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
7.677 1.388 tCL FF u_Gowin_PLLVR/pllvr_inst/CLKOUTD
7.940 0.262 tNET FF u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_3_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 u_Gowin_PLLVR/pllvr_inst/CLKOUTD.default_gen_clk
13.967 1.388 tCL RR u_Gowin_PLLVR/pllvr_inst/CLKOUTD
14.151 0.185 tNET RR u_HyperRAM_Memory_Interface_Top/u_hpram_top/u_hpram_sync/lock_cnt_3_s3/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
843 user_clk -5.405 0.257
378 ddr_rsti -0.384 1.813
310 sys_clk_d -12.784 1.727
145 rd_ptr[2] 4.250 3.923
143 S_ahb_address[2] -10.492 3.767
99 wire_init -3.974 3.279
83 S_ahb_address[4] -10.643 4.418
77 S_ahb_address[3] -12.784 7.398
74 rd_ptr[1] 5.482 2.655
68 S_wr_state_0[0] -0.359 4.569

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R13C26 75.00%
R8C7 73.61%
R15C26 68.06%
R6C1 68.06%
R15C27 63.89%
R11C16 61.11%
R9C32 59.72%
R8C1 58.33%
R13C27 56.94%
R11C17 56.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name SYS_CLK -period 37.037 -waveform {0 18.518} [get_ports {sys_clk}]